Switched capacitor circuit implementations of pipelined analog-to-digital converters (ADCs) employ non-overlapping clock signals for operation. Conventional clock generation techniques are highly dependant on process and temperature. Here, the non-overlap is supposed to be a fraction of the clock period across process and temperature. The non-overlap period keeps increasing with the clock period TS (where TS=1 FS with FS being ADC's operating speed). So the time available to charge the sampling capacitor to input voltage (sample-time) and the time available for the amplifier in the multiplying digital-to-analog converter (MDAC) to settle to its final value (hold-time) remain a constant fraction of the clock period TS. A significant fraction of the total power in a pipelined ADC is spent on the amplifiers in the MDACs to obtain acceptable bandwidths (acceptable settling errors).
Several different clock generation techniques exist. An example is a delay locked loop (DLL). Turning to FIG. 1A, an example of a conventional DLL 100 can be seen. DLL 100 generally comprises a duty cycle controller 102, a delay line 104, a phase detector (PD) 106, a charge pump, and a loop filter. As shown, delay line 104 is generally comprised of delay elements 112-1 to 112-N coupled in series with one another, while the charge pump is generally comprised of switches S1 and S2 and current sources 108 and 110. In operation, the duty cycle controller 102 receives a clock signal with a period TS and provides a clock signal CLKIN to the PD 106 and delay line 104, and the delay line 104 provides a feedback signal FB to the PD 106 from one of its delay elements 112-1 to 112-N. Based on the feedback signal FB and the clock signal CLKIN, the PD 106 generates symmetrical pulses for switches S1 and S2 so that current sources 108 and 110 (which each provide currents having the same general magnitude) can drive a current onto a plate of capacitor CF, resulting in a particular control voltage VCNTL on control node NCNTL. This control voltage VCNTL is then provided to each of the delay elements 112-1 to 112-N so as to control the operation of the delay line 104.
For an example operation of conventional DLL 100, assume that output edges to be at
      T    S    26apart (which can be seen in FIG. 1B), the delay line would have 13 delay elements or buffers (i.e., 112-1 to 112-13). If the output of the first through thirteenth buffers are referred to as d1 to d13 (respectively), PD 106 of DLL 100 would compare the clock signal CLKIN to the output from the thirteenth delay element d13. When DLL 100 has converged such that the control voltage VCNTL has stabilized, up and down pulses provided to switches S1 and S1 of DLL 100 are of equal width or are symmetrical (very small compared to period TS) and would be overlapping.
Some other conventional circuits are: U.S. Pat. No. 7,479,816; U.S. Pat. No. 4,922,141; U.S. Pat. No. 7,567,103; U.S. Patent Pre-Grant Publ. No. 2008/0130177; and U.S. Patent Pre-Grant Publ. No. 2006/0045222.